2023: Bihar Engineering University, Patna End Semester Examination – 2023, Code: 105401
- A pipeline stage
- (i) Is sequential circuit
- (ii) Is combination circuit
- (iii) Consists of both sequential and combinational circuit
- (iv) None of these
Explanation: A pipeline stage typically includes both combinational logic for processing and sequential elements (like registers or latches) to hold data between stages. - A direct mapped cache memory with n blocks is nothing but which of the following set associative cache memory originations
- (i) 0-way set associative
- (ii) 1-way set associative
- (iii) 2-way set associative
- (iv) n-way set associative
Explanation: In a direct-mapped cache, each memory block has only one possible location in the cache (a set of size 1), making it a 1-way set-associative cache. - The performance of a pipelined processor suffers if
- (i) The pipeline stages have different delays
- (ii) Consecutive instruction are dependent on each other
- (iii) The pipeline stages share hardware resources
- (iv) All of these
Explanation: All the mentioned factors (uneven stage delays, data dependencies causing stalls, and structural hazards due to shared resources) reduce the performance of a pipelined processor. - A computer with cache access time of 100 ns, a main memory access time of 1000 ns, and a hit ratio of 0.9 produces an average access time of
- (i) 250 ns
- (ii) 200 ns
- (iii) 190 ns
- (iv) None of these
Explanation: Average access time = (Hit Ratio * Cache Access Time) + ((1 – Hit Ratio) * Main Memory Access Time) = (0.9 * 100) + (0.1 * 1000) = 90 + 100 = 190ns - Which of the following has no practical usage?
- (i) SISD
- (ii) SIMD
- (iii) MISD
- (iv) MIMD
Explanation: MISD (Multiple Instruction, Single Data) architectures have limited practical applications. - A micro programmed control unit
- (i) Is faster than a hardwired control unit
- (ii) Facilitates easy implementation of new instructions
- (iii) Is useful when every small program is to be run
- (iv) Usually refers to the control unit of the microprocessor
Explanation: Microprogrammed control units make it easier to modify or add new instructions compared to hardwired control units. - In memory- mapped I/O
- (i) The I/O devices and the memory share the same address space.
- (ii) The I/O device have a separate address space
- (iii) The memory and I/O device have an associated address space
- (iv) A part of the memory is specifically set aside for the I/O operation
Explanation: In memory-mapped I/O, I/O devices are accessed using the same memory addressing scheme as regular memory locations. - How many 128×8 bit RAMs are required to design 32 k x 32 bit RAM?
- (i) 512
- (ii) 128
- (iii) 1024
- (iv) 32
Explanation:- 32k = 32 * 1024 = 32768
- 128 x 8 bit = 128 * 8 = 1024 bits.
- 32768 * 32 bits / 128 * 8 bits = 32. So, 32 number of Rams are required.
- The stalling of the processor due to the unavailability of the instruction is called as
- (i) Control hazard(ii) Structural hazard(iii) Input hazard(iv) None of the above
Explanation: A control hazard (or branch hazard) occurs when the CPU does not know which instruction to fetch next, typically due to branching or jumps. - The addressing mode, where you directly specify the operand value is
- (i) Immediate
- (ii) Direct
- (iii) Definite
- (iv) Relative
Explanation: In immediate addressing, the operand value is directly included in the instruction itself.
2022: B.Tech 4th Semester Exam., 2022, Code: 105401/106401
- The 8-bit encoding format used to store data in a computer is
- (i) ASCII
- (ii) EBCDIC
- (iii) ANCI
- (iv) USCII
- The bus used to connect the monitor to the CPU is
- (i) PCI bus
- (ii) SCSI bus
- (iii) memory bus
- (iv) ram bus
- The alternate way of writing the instruction, ADD #5, R1 is
- (i) ADD [5],[R1];
- (ii) ADDI 5,R1
- (iii) ADDIME 5,[R1];
- (iv) There is no other way
- The instruction fetch phase ends with
- (i) placing the data from the address in MAR into MDR
- (ii) placing the address of the data into MAR
- (iii) completing the execution of the data and placing its storage address into MAR
- (iv) decoding the data in MDR and placing it in IR
- For converting a virtual address into the physical address, the programs are divided into
- (i) pages
- (ii) frames
- (iii) segments
- (iv) blocks
- The transfer of large chunks of data with the involvement of the processor is done by
- (i) DMA controller
- (ii) arbitrator
- (iii) user system programs
- (iv) None of the above
- The computer architecture aimed at reducing the time of execution of instructions is
- (i) CISC
- (ii) RISC
- (iii) ISA
- (iv) ANNA
- Which table handle stores the addresses of the interrupt handling sub-routines?
- (i) Interrupt-vector table
- (ii) Vector table
- (iii) Symbol link table
- (iv) None of the above
- The situation wherein the data of operands are not available is called
- (i) data hazard
- (ii) stock
- (iii) deadlock
- (iv) structural hazard
- The DMA controller has registers.
- (i) 4
- (ii) 2
- (iii) 3
- (iv) 1
2019: B.Tech 6th Semester Exam., 2019 Code : 051602
- The instruction, Add#45, R1 does
- (i) adds the value of 45 to the address of R1 and stores 45 in that address
- (ii) adds the value of 45 to the register and stores it in R1
- (iii) finds the memory location 45 and adds that content to the register
- (iv) None of the above
- The usual BUS structure used to connect the 1/O devices is
- (i) star BUS structure
- (ii) multiple BUS structure
- (iii) single BUS structure
- (iv) node to node BUS structure
- Any condition that causes a processor to stall is called as
- (i) hazard
- (ii) page fault
- (iii) system error
- (iv) None of the above
- The stalling of the processor due to the unavailability of the instructions is called as
- (i) control hazard(ii) structural hazard(iii) input hazard(iv) None of the above
- After the completion of the DMA transfer the processor is notified by
- (i) Acknowledge signal(ii) interrupt signal(iii) WMFC signal(iv) None of the above
2017: B.Tech 6th Semester Examination, 2017
- The DMA differs from the interrupt mode by
- (i) The involvement of the processor for the operation
- (ii) The method accessing the I/O devices
- (iii) The amount of data transfer possible
- (iv) Both (i) and (iii)
- When generating physical addresses from logical address the offset is stored in
- (i) Translation look-aside buffer
- (ii) Relocation register
- (iii) Page table
- (iv) Shift register
- (c) The computer architecture aimed at reducing the time of execution of instructions is……..
- (i) CISC
- (ii) RISC
- (iii) ISA
- (iv) ANNA
- (d) In DMA transfers, the required signals and addresses are given by the………
- (i) Processor
- (ii) Device drivers
- (iii) DMA controllers
- (iv) The program itself
- (e) Both the CISC and RISC architectures have been developed to reduce the……..
- (i) Cost
- (ii) Time delay
- (iii) Semantic gap
- (iv) All of the above
- (f) In pipelining the task which requires the least time is performed first
- (i) True
- (ii) False
- (g) The DMA controller has…………registers.
- (i) 4
- (ii) 2
- (iii) 3
- (iv) 1
- (h) In memory-mapped I/O……..
- (i) The I/O devices and the memory share the same address space.
- (ii) The I/O devices have a separate address space.
- (iii) The memory and I/O devices have an associated address space
- (iv) A part of the memory is specifically set aside for the I/O operation
- (i) Any condition that causes a processor to stall is called as……
- (i) Hazard(ii) Page fault(iii) System error(iv) None of the above
- (j) The situation where in the data of operands are not available is called………..
(i) Data hazard(ii) Stock(iii) Deadlock(iv) Structural hazard
B.Tech 6th Semester Examination, 2018
(a) Which among the following can be considered as most advanced ROM?
- (i) DRAM
- (ii) EEPROM
- (iii) RAM
- (iv) PROM
- Answer: (ii) EEPROM
- Explanation:
- DRAM (Dynamic RAM) and RAM (Random Access Memory) are volatile memories used for main memory, not ROM (Read-Only Memory).
- PROM (Programmable ROM) can be programmed once.
- EEPROM (Electrically Erasable Programmable ROM) can be erased and reprogrammed electrically, making it the most advanced of the ROM types listed.
(b) Where the results of arithmetic and logical operations are stored?
- (i) In accumulator
- (ii) In cache memory
- Answer: (i) In accumulator
- Explanation: The accumulator is a register within the CPU that stores intermediate results during arithmetic and logical operations. Cache memory is used for storing frequently accessed data for faster retrieval.
(c) Which determines the address of I/O interface?
- (i) Register select
- (ii) Chip select
- (iii) Both (i) and (ii)
- (iv) None of the above
- Answer: (iii) Both (i) and (ii)
- Explanation: Chip select is a signal used to select a specific I/O device. Register select is used to select a particular register within that I/O device. Both are needed to uniquely address an I/O interface.
(d) Whenever CPU detects an interrupt, what it does with the current state?
- Save it
- (ii) Discard it
- (iii) Depends system to system
- (iv) First finish it
- Answer: Save it
- Explanation: Before handling an interrupt, the CPU must save the current state (program counter, registers, etc.) so that it can resume execution of the interrupted program later.
(e) ___ reads the data by reflecting pulses of laser beams on the surface.
- (i) Magnetic disk
- (ii) Optical disk
- (iii) Floppy disk
- (iv) ROM
- Answer: (ii) Optical disk
- Explanation: Optical disks (like CDs, DVDs, and Blu-rays) store data by encoding it as patterns that reflect or scatter laser light. Magnetic disks use magnetic fields, floppy disks are older magnetic storage, and ROM is a memory type.
(f) The instruction, Add#45, R1 does
- (i) adds the value of 45 to the address of R1 and stores 45 in that address
- (ii) adds 45 to the value of R1 and stores it in R1
- (iii) finds the memory location 45 and adds that content to that of R1
- (iv) None of the above
- Answer: (iii) finds the memory location 45 and adds that content to that of R1
- Explanation: The # symbol typically indicates an immediate operand or memory address. Thus, the instruction retrieves the value stored at memory address 45 and adds it to the contents of register R1.
(g) The usual BUS structure used to connect the I/O devices is
- (i) star BUS structure
- (ii) multiple BUS structure
- (iii) single BUS structure
- (iv) node to node BUS structure
- Answer: (iii) single BUS structure
- Explanation: A single bus structure is a common and simple method to connect I/O devices to the CPU. It allows multiple devices to share the same communication channel.
(h) Any condition that causes a processor to stall is called as
- (i) hazard
- (ii) page fault
- (iii) system error
- (iv) None of the above
- Answer: (i) hazard
- Explanation: Hazards are situations that prevent the next instruction in the instruction stream from executing during its designated clock cycle. Page faults and system errors are distinct types of exceptional conditions.
(i) The stalling of the processor due to the unavailability of the instructions is called as
- (i) control hazard
- (ii) structural hazard
- (iii) input hazard
- (iv) None of the above
- Answer: (i) Control hazard
- Explanation: A control hazard (or branch hazard) occurs when the CPU does not know which instruction to fetch next, typically due to branching or jumps.
(j) After the completion of the DMA transfer the processor is notified by
- (i) acknowledge signal
- (ii) interrupt signal
- (iii) WMFC signal
- (iv) None of the above
- Answer: (ii) Interrupt signal
- Explanation:After DMA transfer completes, the DMA controller sends an interrupt to notify the CPU.
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